1. Field of the Invention
This invention relates to the effect of power supply noise on electrical circuits on a die, and more specifically to optimization of the clock distribution on the die to reduce the effect of power supply noise.
2. Background
Electronic devices, such as microprocessors, are steadily operating at faster and faster speeds. As microprocessors run at higher and higher speeds, the power delivered to the microprocessor by a power supply starts to become an issue. As power is delivered from a power source to the individual components and devices on the die of a microprocessor, voltage drops occur. For example, devices on a die may receive only 1.0 volt from a power source that is supplying 1.2 volts due to a voltage droop. Decoupling capacitors are used on a die to help reduce voltage droop. However, decoupling capacitors cost area on the die and also cost power due to gate oxide leakage.
Power source voltage droops affect the speed at which an electronic device (e.g., microprocessor) may operate. During normal operation of a microprocessor (or any sequential machine), noise is generated from instantaneous switching. Voltage supply noise modulates the delay of data paths. Voltage droops reduce the maximum frequency of operation of the microprocessor. As microprocessor speeds increase, the voltage droop magnitude increases and the maximum frequency of the microprocessor is further adversely affected. The clock distribution delay is also modulated by this supply noise. Moreover, clock period modulation may also be detrimental to maximum frequency of operation.
Therefore, a need exists for method and apparatus that provide design of a circuit on with higher tolerance to power supply noise.